In the fabrication of an integrated circuit, physical verification of the circuit layout is an important process, and is particularly vital during the early stages of technology development in which circuits intended for technology ramp-up and device modeling are produced. Layout versus schematic (LVS) comparison is a well-known computerized verification method for determining whether a netlist generated from a circuit layout corresponds to an input schematic diagram/design for the intended circuit. However, LVS techniques are not always efficient, especially when dealing with circuit layouts with large arrays of devices. In those cases, manual processes can be performed to verify a circuit layout, but manual verification introduces its own disadvantages. What is needed is an efficient automated verification technique for verifying circuit layouts having arrays of potentially millions of devices.